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[AKD4648-C]
AKD4648-C
Evaluation board Rev.1 for AK4648
GENERAL DESCRIPTION AKD4648 is an evaluation board for the AK4648, stereo CODEC with MIC/HP/SPK amplifier. The AKD4648 can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D D/A). The AKD4648 also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide
AKD4648 --Evaluation board for AK4648 (Cable, USB interface board for connecting with USB port, and control software are packed with this. This control software does not support Windows NT.)
FUNCTION * DIT/DIR with optical input/output * 10pin Header for digital audio interface * 10pin Header for serial control mode
VCC
Regulator 3.3 V
TVDD
HVDD MIC MIN LINE IN
AVDD
DVDD
TVDD
D3V
PORT1
DIR Opt In
AK4115
DIT Opt out
PORT2
HP LINE OUT SPK
AK4648
DSP 10pin Header
PORT3
Control Data 10pin Header AGND
PORT4
Figure 1. AKD4648-C Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual
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Evaluation Board Manual Operation sequence
(1) Set up the power supply lines. (1-1) In case of using the regulator. (1-1-1) TVDD is supplied from the regulator. Set up the jumper pins. JP22 JP REG_SEL State REG JP23 TVDD_SEL Short
Set up the power supply lines. [VCC] (red) = 4.3 ~ 5.0V : typ. 4.5V for regulator and HVDD of AK4648 (regulator 3.3V output : AVDD, DVDD and TVDD of the AK4648 and logic) [TVDD] (orange) = Open [AGND] (black) = 0V : for analog ground [DGND] (black) = 0V : for logic ground (1-1-2) TVDD is supplied from the power supply connector of "TVDD". Set up the jumper pins. JP22 JP REG_SEL State REG JP23 TVDD_SEL Open
Set up the power supply lines. [VCC] (red) = 4.3 ~ 5.0V : typ. 4.5V for regulator and HVDD of AK4648 (regulator 3.3V output : AVDD and DVDD of the AK4648 and logic) [TVDD] (orange) = 1.6 ~ 3.6V : typ. 3.3V for TVDD of AK4648 (TVDD DVDD) [AGND] (black) = 0V : for analog ground [DGND] (black) = 0V : for logic ground (1-2) When the regulator is not used. Set up the jumper pins. JP22 JP REG_SEL State VCC JP23 TVDD_SEL Open
Set up the power supply lines. [VCC] (red) = 2.6 ~ 3.6V [TVDD] (orange) = 1.6 ~ 3.6V [AGND] (black) = 0V [DGND] (black) = 0V
: typ. 3.3V for AVDD, DVDD and HVDD of AK4648 and logic : typ. 3.3V for TVDD of AK4648 (TVDD DVDD) : for analog ground : for logic ground
* Each supply line should be distributed from the power supply unit. (2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) (3) Power on. The AK4648 and AK4115 should be reset once bringing SW1 (PDN) "L" upon power-up. -22007/04
[AKD4648-C]
Evaluation mode
In case of AK4648 evaluation using AK4115, it is necessary to correspond to audio interface format for AK4648 and AK4115. About AK4648's audio interface format, refer to datasheet of AK4648. About AK4115's audio interface format, refer to Table 2 on page 11 in this manual. Sampling frequency (fs) of AK4115 is 22kHz or more. If the fs is slower than 22kHz, please use other mode. In addition, MCLK of AK4115 supports 256fs and 512fs. When evaluating it in a condition except this, please use other mode.
(1) External Slave Mode (1-1) Evaluation of A/D using DIT of AK4115 (1-2) Evaluation of D/A using DIR of AK4115 (1-3) Evaluation of Loop-back using AK4115 (1-4) All interface signals are fed externally (2) External Master Mode (2-1) Evaluation of A/D using DIT of AK4115 (2-2) Evaluation of D/A using DIR of AK4115 (2-3) Evaluation of Loop-back using AK4115 (2-4) All interface signals are fed externally (3) PLL Slave Mode (3-1) Reference Clock : MCKI pin (3-1-1) Evaluation of A/D using DIT of AK4115 (3-1-2) Evaluation of Loop-back using AK4115 (3-1-3) All interface signals are fed externally (3-2) Reference Clock : BICK or LRCK pin (3-2-1) Evaluation of A/D using DIT of AK4115 (3-2-2) Evaluation of D/A using DIR of AK4115 (3-2-3) Evaluation of Loop-back using AK4115 (3-2-4) All interface signals are fed externally (4) PLL Master Mode (4-1) Evaluation of A/D using DIT of AK4115 (4-2) Evaluation of Loop-back using AK4115 (4-3) All interface signals are fed externally
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(1)
External Slave Mode (1-1) Evaluation of A/D using DIT of AK4115 PORT2 (DIT) and X1 (X'tal) are used. DIT generates audio bi-phase signal from received data and which is output through optical connector (TOTX141). Nothing should be connected to PORT1 (DIR) and PORT3 (DSP). The jumper pins should be set as follows.
JP14 4115_MCKI
JP15 DIR_MCLK
JP16 BICK
JP17 LRCK
JP19 DIR_SEL Slave Master
(1-2) Evaluation of D/A using DIR of AK4115 PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT3 (DSP). The jumper pins should be set as follows.
JP14 4115_MCKI
JP15 DIR_MCLK
JP16 BICK
JP17 LRCK
JP19 DIR_SEL Slave Master
JP21 SDTI DIR ADC
(1-3) Evaluation of Loop-back using AK4115 X1 (X'tal) is used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP). The jumper pins should be set as follows.
JP14 4115_MCKI
JP15 DIR_MCLK
JP16 BICK
JP17 LRCK
JP19 DIR_SEL Slave Master
JP21 SDTI DIR ADC
(1-4) All interface signals are fed externally PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). The jumper pins should be set follows.
JP20 SDTO-IN
JP15 DIR_MCLK
JP16 BICK
JP17 LRCK
JP19 DIR_SEL Slave Master
JP21 SDTI DIR ADC
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(2)
External Master Mode (2-1) Evaluation of A/D using DIT of AK4115 PORT2 (DIT) and X1 (X'tal) are used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP). In Master Mode, BICK and LRCK of AK4648 should be input to AK4115. Please refer to Table2 on page 11. The jumper pins should be set as follows.
JP14 4115_MCKI
JP15 DIR_MCLK
JP16 BICK
JP17 LRCK
JP19 DIR_SEL Slave Master
(2-2) Evaluation of D/A using DIR of AK4115 PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT3 (DSP). In Master Mode, BICK and LRCK of AK4648 should be input to AK4115. Please refer to Table2 on page 11. The jumper pins should be set as follows.
JP14 4115_MCKI
JP15 DIR_MCLK
JP16 BICK
JP17 LRCK
JP19 DIR_SEL Slave Master
JP21 SDTI DIR ADC
(2-3) Evaluation of Loop-back using AK4115 X1 (X'tal) is used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP). The jumper pins should be set as follows.
JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master JP21 SDTI DIR ADC
(2-4) All interface signals are fed externally PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). The jumper pins should be set as follows.
JP20 SDTO-IN
JP15 DIR_MCLK
JP16 BICK
JP17 LRCK
JP19 DIR_SEL Slave Master
JP21 SDTI DIR ADC
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(3)
PLL Slave Mode (3-1) Reference Clock : MCKI pin (3-1-1) Evaluation of A/D using DIT of AK4115 PORT2 (DIT) and PORT3 (DSP) are used. Nothing should be connected to PORT1 (DIR). The system clock (PLL reference clock) should be connected to MCLK of PORT3. MCKO of AK4648 should be input to AK4115's XTI. X'tal oscillator should be removed from X1. The jumper pins should be set as follows.
JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master JP20 SDTO_IN JP2 JP21 SDTI DIR ADC
RIN3
VCOC
(3-1-2) Evaluation of Loop-back using AK4115 PORT2 (DIT) and PORT3 (DSP) are used. Nothing should be connected to PORT1 (DIR). The system clock (PLL reference clock) should be connected to MCLK of PORT3. MCKO of AK4648 should be input to AK4115's XTI. X'tal oscillator should be removed from X1. The jumper pins should be set as follows.
JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master JP20 SDTO_IN JP2 JP21 SDTI DIR ADC
RIN3
VCOC
(3-1-3) All interface signals are fed externally PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). BICK and LRCK inputs should be synchronized with MCKO of AK4648. MCLK (PLL reference clock), BICK, LRCK and SDTI are supplied from PORT3. The JP14 (4115_MCKI)'s lower side (MCKO of AK4648) should be connected to MCLK of DSP. The jumper pins should be set as follows.
JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master JP20 SDTO_IN JP2 JP21 SDTI DIR ADC
RIN3
VCOC
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(3-2) Reference Clock : BICK or LRCK pin (3-2-1) Evaluation of A/D using DIT of AK4115 X1 (X'tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR). The jumper pins should be set as follows.
JP14 4115_MCKI
JP15 DIR_MCLK
JP16 BICK
JP17 LRCK
JP19 DIR_SEL Slave Master
JP21 SDTI DIR ADC
JP20 SDTO_IN
JP2
RIN3
VCOC
(3-2-2) Evaluation of D/A using DIR of AK4115 PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT3 (DSP). The jumper pins should be set as follows.
JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master JP20 SDTO_IN JP2 JP21 SDTI DIR ADC
RIN3
VCOC
(3-2-3) Evaluation of Loop-back using AK4115 X1 (X'tal) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT), and PORT3 (DSP). The jumper pins should be set as follows.
JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master JP20 SDTO_IN JP2 JP21 SDTI DIR ADC
RIN3
VCOC
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(3-2-4) All interface signals are fed externally PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). BICK, LRCK, and SDTI are supplied from PORT3. The jumper pins should be set as follows.
JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master JP20 SDTO_IN JP2 JP21 SDTI DIR ADC
RIN3
VCOC
(4)
PLL Master Mode (4-1) Evaluation of A/D using DIT of AK4115 PORT2 (DIT) and PORT3 (DSP) are used. Nothing should be connected to PORT1(DIR). The system clock (PLL reference clock) should be connected to MCLK of PORT3. In case of supplying MCKO to DSP, the JP14 (4115_MCKI)'s lower side should be connected to MCLK of DSP. X'tal oscillator should be removed from X1. In Master Mode, BICK and LRCK of AK4648 should be input to AK4115. Please refer to Table2 on page 11. The jumper pins should be set as follows.
JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master
JP20 SDTO_IN JP2
JP21 SDTI DIR ADC
RIN3
VCOC
(4-2) Evaluation of Loop-back PORT2 (DIT) and PORT3 (DSP) are used. Nothing should be connected to PORT1(DIR). The system clock (PLL reference clock) should be connected to MCLK of PORT3. In case of supplying MCKO to DSP, the JP14 (4115_MCKI)'s lower side should be connected to MCLK of DSP. X'tal oscillator should be removed from X1. The jumper pins should be set as follows.
JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master JP20 SDTO_IN JP2 JP21 SDTI DIR ADC
RIN3
VCOC
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(4-3) All interface signals are fed externally PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). The system clock (PLL reference clock) should be connected to MCLK of PORT3. In case of supplying MCKO to DSP, the JP14 (4115_MCKI)'s lower side should be connected to MCLK of DSP. X'tal oscillator should be removed from X1. The jumper pins should be set as the follows.
JP14 4115_MCKI
JP15 DIR_MCLK
JP16 BICK
JP17 LRCK
JP19 DIR_SEL Slave Master
JP21 SDTI DIR ADC
JP20 SDTO_IN
JP2
RIN3
VCOC
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DIP Switch set up
[S1] (SW DIP1-4): Mode setting for AK4648 and AK4115. No. 1 2 3 4 Name CAD0 OCKS1 DIF0 DIF1 ON ("H") OFF ("L") AK4648 Chip Address Setting: (See Table 4) AK4115 Master Clock Setting: (See Table 3) AK4115 Audio Format Setting See Table 2 Table 1. Mode Setting for AK4648 and AK4115 Default OFF OFF OFF OFF
Mode 1 2 3 4
DIF1 0 0 1 1
DIF0 0 1 0 1
DAUX
SDTO
LRCK
I/O
BICK
I/O
24bit, Left justified 24bit, Left justified H/L O 24bit, I2S 24bit, I2S L/H O 24bit, Left justified 24bit, Left justified H/L I 24bit, I2S 24bit, I2S L/H I Table 2. Setting for AK4115 Audio Interface Format Mode 0 1 OCKS1 0 1 MCKO1 pin 256fs 512fs X'tal 256fs 512fs
64fs 64fs 64-128fs 64-128fs
O O I I
Table 3. Setting for AK4115 Master Clock
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Other jumper pins set up
[JP1] (GND) : Analog ground and Digital ground. SHORT : Common. (The connector "DGND" can be open.) OPEN : Separated. [JP2] : Selection of RIN3 path or PLL Mode. RIN3 : RIN3 path. VCOC : PLL Mode. [JP4] (LIN1) : Selection of using MIC-power supply for LIN1. SHORT : MIC-power is supplied. OPEN : MIC-power is not supplied. [JP7] (RIN1) : Selection of using MIC-power supply for RIN1. SHORT : MIC-power is supplied. OPEN : MIC-power is not supplied. [JP8] (LIN2) : Selection of using MIC-power supply for LIN2. SHORT : MIC-power is supplied. OPEN : MIC-power is not supplied. [JP9] (RIN2) : Selection of using MIC-power supply for RIN2. SHORT : MIC-power is supplied. OPEN : MIC-power is not supplied. [JP12] : Selection of LIN3 path or MIN path. SHORT : LIN3 path. OPEN: MIN path. [JP14] (4114_MCKI) : AK4115 Clock Source. OPEN : X'tal of AK4115 is used. SHORT : MCKO of AK4648 (X'tal oscillator should be removed from X1). [JP18] (Signal V_select) : Selection of power supply for logic(U4). D3V : It is supplied from D3V. TVDD : It is supplied from TVDD. [JP20] (SDTO_IN) : SDTO of PORT3. SHORT : It supply SDTO to PORT3. OPEN : It does not supply SDTO to PORT3.
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The function of the toggle SW
[SW1] (PDN): Power down of AK4648. Keep "H" during normal operation. [SW2] (DIR): Power down of AK4115. Keep "H" during normal operation. Keep "L" when AK4115 is not used. *Upper-side is "H" and lower-side is "L".
Indication for LED
[LED1] (ERF): Monitor INT0 pin for the AK4115. LED turns on when some error has occurred to AK4115.
Serial Control
The AKD4648-C can be connected via the USB port with attached USB interface board. Connect PORT4 (CTRL) with PC by 10 wire flat cable packed with the AKD4648-C. Table 4 shows switch and jumper settings for serial control. Note) When I2C-bus is controlled by P via PORT4, resistor value of R100 should be properly selected.
PORT4
1 10
for PC
USB I/F Board
Connect
SCL SDA
6
USB Cable 10 wire flat cable 10pin Connector
5
AKD4648-C
10pin Header
Figure 2. Connect of 10 wire flat cable
Mode I2C CAD0=0 CAD0=1
S1 CAD0 OFF ON
Default
Table 2. Serial Control Setting
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Analog Input/Output Circuits
(1) Input Circuits Input Circuits of LIN1/RIN1, LIN2/RIN2, LIN3/RIN3, LIN4/RIN4, and MIN.
J1 LIN1/RIN1 6 + 4 3 C15 1u LIN1 + R12 2.2k C13 1u RIN1
JP4
LIN1 JP7 R13 2.2k
RIN1 JP8 LIN2 JP9 RIN2 J3 LIN2/RIN2 6 + 4 3 C20 1u LIN2 + C19 1u RIN2 R17 2.2k R16 2.2k MPWR
C21 1u J5 MIN/LIN3/RIN3 6 4 3 RIN3 C22 1u + MIN/LIN3 R18 20k + LIN3 JP12
C23 1u J8 LIN4/RIN4 6 4 3 RIN4 C25 1u LIN4 + +
Figure 3. Input circuits LIN1/RIN1, LIN2/RIN2, LIN3/RIN3, LIN4/RIN4, and MIN
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When LIN3/RIN3 paths of AK4648 are used, JP2 and JP12 should be set as follows. AIN3 bit = "1" (Register Address 21H)
JP12 LIN3 JP2
RIN3
VCOC
When MIN path of AK4648 is used, JP12 should be set as follows. AIN3 bit = "1" (Register Address 21H)
JP12 LIN3
When MIC- power output (MPWR pin) of AK4648 is used, JP4 (LIN1) / JP7 (RIN1) and / or JP8 (LIN2) / JP9 (RIN2) should be short.
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(2) Output Circuits (2-1) HP Output Circuit
JP3 HPR Cap-less
C14 220u
+ HPR
R10
short
6 4 3 J2 HP
HPL
+
C16 220u
C17 0.22u C18 0.22u JP5 HPL Cap-less R14 10 R15 10
R11
short
HVCM
JP6
GND
HVCM
Figure 4. HP Output Circuit
(2-1-1) Single-ended Mode The jumper pins should be set as follows.
JP3 HPR Cap-less
JP5 HPL Cap-less
JP6
HVCM
GND
(2-1-2) Pseudo Cap-less Mode The jumper pins should be set as follows.
JP3 HPR Cap-less
JP5 HPL Cap-less
JP6
HVCM
GND
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(2-2) LOUT/ROUT Output Circuit
+
C24 1u 6 4 3 JP13 LINEOUT
J7 LOUT/ROUT
ROUT R19 LOUT 1u C26 +
open
Figure 5. LOUT/ROUT Output Circuit
The jumper pins should be set as follows.
JP13 LINEOUT
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(2-3) SPK Output Circuit
TP1 SPLP
J4 6 4 3 1
SPK/L
SPLN SPLP
1 JP10 High SPN TP3 SPRP TP2 SPLN JP11 High SPP
J6 6 4 3 1
SPK/R
SPRN SPRP
1
TP4 SPRN
Figure 6. SPK Output Circuit
(2-3-1) Stereo SPK Mode The jumper pins should be set as follows.
JP10 High SPN
JP11 High SPP
(2-3-2) Mono SPK Mode The jumper pins should be set as follows.
JP10 High SPN
JP11 High SPP
(2-3-3) High Power SPK Mode The jumper pins should be set as follows.
JP10 High SPN
JP11 High SPP
AKM assumes no responsibility for the trouble when using the above circuit examples.
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Control Software Manual Set-up of evaluation board and control software
1. Set up the AKD4648-C according to previous term. 2. Connect IBM-AT compatible PC with AKD4648-C by 10-line type flat cable via the USB port with attached USB interface board (packed with AKD4648-C). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer "Installation Manual of Control Software Driver by AKM device control software". In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled "AKD4648-C Evaluation Kit" into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of "AKD4648.exe" to set up the control program. 5. Then please evaluate according to the follows.
Operation flow
Keep the following flow. 1. Set up the control program according to explanation above. 2. Click "Port Reset" button.
Explanation of each buttons
[Port Reset] : [Write default] : [All Write] : [Function1] : [Function2] : [Function3] : [Function4] : [Function5]: [SAVE] : [OPEN] : [Write] : [Filter] : [5 Band EQ] : Set up the USB interface board (AKDUSBIF-A) . Initialize the register of AK4648. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Set Programmable Filter (FIL1, FIL3, EQ) of AK4648. Set 5-Band Equalizer of AK4648.
Indication of data
Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". Blank is the part that is not defined in the datasheet.
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Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". If you want to write the input data to AK4648, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal.
If you want to write the input data to AK4648, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Dialog to evaluate IVOL and DVOL
Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4648 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK4648, click [OK] button. If not, click [Cancel] button.
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4. [Save] and [Open] 4-1. [Save]
Save the current register setting data. The extension of file name is "akr". (Operation flow) (1) Click [Save] Button. (2) Set the file name and push [Save] Button. The extension of file name is "akr". 4-2. [Open] The register setting data saved by [Save] is written to AK4648. The file type is the same as [Save]. (Operation flow) (1) Click [Open] Button. (2) Select the file (*.akr) and Click [Open] Button.
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5. [Function3 Dialog]
The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set "-1" to the address of the step where the sequence should be paused. (3) Click [Start] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of file name is "aks".
Figure 7. Window of [F3]
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6. [Function4 Dialog]
The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the
window as shown in Figure 8 opens.
Figure 8. [F4] window
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6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks). The sequence file name is displayed as shown in Figure 9.
Figure 9. [F4] window(2) (2) Click [START] button, then the sequence is executed.
3-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The sequence file names can assign be saved. The file name is *.ak4. [OPEN] : The sequence file names assign that are saved in *.ak4 are loaded.
3-3. Note
(1) This function doesn't support the pause function of sequence function. (2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change.
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7. [Function5 Dialog] The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When [F5] button is clicked, the following window as shown in Figure 10 opens.
Figure 10. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr).
The register setting file name is displayed as shown in Figure 11. (2) Click [WRITE] button, then the register setting is executed.
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Figure 11. [F5] windows(2)
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The register setting file names assign can be saved. The file name is *.ak5. [OPEN] : The register setting file names assign that are saved in *.ak5 are loaded.
7-3. Note
(1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to reflect the change.
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8. [Filter Dialog] This dialog can easily set the AK4648's programmable filter.
Figure 12. [Filter] window
8-1. Value input columns on left side
[Sampling Rate] [Cut Off Frequency of FIL1] [Cut Off Frequency of FIL3] [Pole Frequency of EQ] [Zero Frequency of EQ] [FIL3 GAIN] [EQ GAIN] Input value of sampling frequency [unit : Hz] Input value of cut off frequency of FIL1 [unit : Hz] Input value of cut off frequency of FIL3 [unit : Hz] Input value of pole frequency of EQ [unit : Hz] Input value of zero frequency of EQ [unit : Hz] Input value of gain of FIL3 (0~-10dB) [unit : dB] Input value of gain of EQ (+12~0dB) [unit : dB]
8-2. Check box on left side
Check Box FIL1 FIL3 EQ LPF of FIL1 LPF of FIL3 Check FIL1 bit ="1" FIL3 bit ="1" EQ bit ="1" F1AS bit ="1"(LPF) F3AS bit ="1"(LPF) Check off FIL1 bit ="0" FIL3 bit ="0" EQ bit ="0" F1AS bit ="0"(HPF) F3AS bit ="0"(HPF)
8-2. [Register Setting] panel and [Register Setting] button on right side
Click [Register setting] button, then filter coefficient set by 8-1 and 8-2 is written on [Register setting] panel. (It is also written to the actual control register of the AK4648.)
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9. [5 Band EQ Dialog] This dialog can easily set the AK4648's 5-Band Equalizer.
Figure 13. [5 Band EQ] window When the check box of "5 Band EQ" is checked, 5-Band Equalizer is ON (FBEQ bit = "1"). When the slide button is changed, its value is written to the internal register immediately.
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[AKD4648-C]
MEASUREMENT RESULTS
[Measurement condition]
Measurement unit: Audio Precision, System two Cascade Dual Domain EXT Slave Mode BICK: 64fs Bit: 16bit Measurement Frequency: <10Hz 20kHz (ADC) <10Hz 22kHz (DAC) Power Supply: AVDD=DVDD=TVDD=3.3V, HVDD=4.5V Temperature: Room Input Frequency: 1kHz Sampling Frequency: 44.1kHz
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1.
TABLE DATA ADC +20dB 83.2 86.5 86.5 IVOL)
ADC (LIN2/RIN2) characteristics (IVOL=0dB, ALC = OFF, LIN2/RIN2 Parameter MIC-Amp Gain S/(N+D) 20kHzLPF (-1dB) D-range 20kHzLPF + A-weighted S/N 20kHzLPF + A-weighted 0dB 88.6 95.2 95.3 Lch [dB] +20dB 83.2 86.5 86.5 Rch [dB] 0dB 88.5 95.2 95.3
DAC (LOUT/ROUT) characteristics (DAC Parameter Lch [dB] S/(N+D) 20kHzLPF (-3dB) 87.5 S/N A-weighted 92.3
LOUT/ROUT) Rch [dB] 87.4 92.3
DAC (HP(Single-ended Mode)) characteristics (DAC-->HP(Single-ended Mode)), RL=16 Parameter Lch [dB] Rch [dB] S/(N+D) 20kHzLPF (-3dB) (HPG=0dB) 69.4 69.5 S/N A-weighted 91.1 91.1
DAC (HP(Pseudo Cap-less Mode)) characteristics (DAC-->HP(Pseudo Cap-less Mode)), RL=16 Parameter Lch [dB] Rch [dB] S/(N+D) 20kHzLPF (-3dB) (HPG=0dB) 64.7 65.0 S/N A-weighted 90.1 90.1
DAC (SP(Stereo)) characteristics (DAC-->SP(Stereo)), RL=8 Parameter Lch [dB] Rch [dB] 20kHzLPF (-0.5dBFS) S/(N+D) 61.5 61.6 (SPKG2-0:+4.43dB) S/N A-weighted 90.4 90.3
DAC (SP(High Power Mode)) characteristics (DAC-->SP(High Power Mode)), RL=8 Parameter [dB] 20kHzLPF (-0.5dBFS) 61.5 S/(N+D) (SPKG2-0:+4.43dB) S/N A-weighted 91.4
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[AKD4648-C]
2. PLOT DATA 2-1 ADC (LIN2/RIN2 ADC)(MIC-Amp Gain:+20dB)
AK4648 LIN2/RIN2 => ADC (MGAIN+20dB) THD + N vs Input Level, fs=44.1kHz, fin=1kHz
-60 -62 -64 -66 -68 -70 -72 -74 -76 d B F S -78 -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 -120 -110 -100 -90 -80 -70 -60 dBr -50 -40 -30 -20 -10 +0
Figure 14. THD+N vs. Input Level
AK4648 LIN2/RIN2 => ADC (MGAIN+20dB) THD + N vs Input Frequency, fs=44.1kHz, -1dB Input
-60 -62 -64 -66 -68 -70 -72 -74 -76 d B F S -78 -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 15. THD+N vs. Input Frequency
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AK4648 LIN2/RIN2 => ADC (MGAIN+20dB) Linearity, fs=44.1kHz, fin=1kHz
+0 -5 -10 -15 -20 -25 -30 -35 -40 d B F S -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -100 -90 -80 -70 -60 -50 dBr -40 -30 -20 -10 +0
Figure 16. Linearity
AK4648 LIN2/RIN2 => ADC (MGAIN+20dB) Frequency Response, fs=44.1kHz, -1dB Input
+0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 d B F S -1.4 -1.6 -1.8 -2 -2.2 -2.4 -2.6 -2.8 -3 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 17. Frequency Response
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[AKD4648-C]
AK4648 LIN2/RIN2 => ADC (MGAIN+20dB) FFT fs=44.1kHz, -1dB Input
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 20
d B F S
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 18. FFT Plot (Input level= -1dBFS)
AK4648 LIN2/RIN2 => ADC (MGAIN+20dB) FFT fs=44.1kHz, -60dB Input
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 20
d B F S
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 19. FFT Plot (Input level= -60dBFS)
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[AKD4648-C]
AK4648 LIN2/RIN2 => ADC (MGAIN+20dB) FFT fs=44.1kHz, No Signal
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 20
d B F S
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 20. FFT Plot (No signal)
AK4648 LIN2/RIN2=>ADC (MGAIN+20dB) Crosstalk, fs=44.1kHz, -1dB Input, red R=>L, blue L=>R
-70 -75 -80 -85 -90 -95 -100 d B -105 -110 -115 -120 -125 -130 -135 -140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 21. Crosstalk Plot
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2007/04
[AKD4648-C]
2-2 ADC (LIN2/RIN2
ADC)(MIC-Amp Gain:0dB)
AK4648 LIN2/RIN2 => ADC (MGAIN 0dB) THD + N vs Input Level , fs=44.1kHz, fin=1kHz
-60 -62 -64 -66 -68 -70 -72 -74 -76 d B F S -78 -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 -100 -90 -80 -70 -60 -50 dBr -40 -30 -20 -10 +0
Figure 22. THD+N vs. Input Level
AK4648 LIN2/RIN2 => ADC (MGAIN 0dB) THD + N vs Input Frequency, fs=44.1kHz, -1dB Input
-60 -62 -64 -66 -68 -70 -72 -74 -76 d B F S -78 -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 23. THD+N vs. Input Frequency
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[AKD4648-C]
AK4648 LIN2/RIN2 => ADC (MGAIN 0dB) Linearity, fs=44.1kHz, fin=1kHz
+0 -5 -10 -15 -20 -25 -30 -35 -40 d B F S -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -100 -90 -80 -70 -60 -50 dBr -40 -30 -20 -10 +0
Figure 24. Linearity
AK4648 LIN2/RIN2 => ADC (MGAIN 0dB) Frequency Response, fs=44.1kHz, -1dB Input
+0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 d B F S -1.4 -1.6 -1.8 -2 -2.2 -2.4 -2.6 -2.8 -3 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 25. Frequency Response
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2007/04
[AKD4648-C]
AK4648 LIN2/RIN2 => ADC (MGAIN 0dB) FFT fs=44.1kHz, -1dB Input
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 20
d B F S
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 26. FFT Plot (Input level= -1dBFS)
AK4648 LIN2/RIN2 => ADC (MGAIN 0dB) FFT fs=44.1kHz, -60dB Input
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 20
d B F S
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 27. FFT Plot (Input level = -60dBFS)
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[AKD4648-C]
AK4648 LIN2/RIN2 => ADC (MGAIN 0dB) FFT fs=44.1kHz, No Signal
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 20
d B F S
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 28. FFT Plot ( No signal )
AK4648 LIN2/RIN2 => ADC (MGAIN 0dB) Crosstalk, fs=44.1kHz, -1dB Input, red R=>L, blue L=>R
-70 -75 -80 -85 -90 -95 -100 d B -105 -110 -115 -120 -125 -130 -135 -140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 29. Crosstalk Plot
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2007/04
[AKD4648-C]
2-3 DAC (DAC
LOUT/ROUT)
AK4648 DAC => LINEOUT THD + N vs Input Level , fs=44.1kHz, fin=1kHz
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -120
d B r A
-110
-100
-90
-80
-70
-60 dBFS
-50
-40
-30
-20
-10
+0
Figure 30. THD+N vs. Input Level
AK4648 DAC => LINEOUT THD + N vs Input Frequency, fs=44.1kHz, 0dB Input
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 20
d B r A
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 31. THD+N vs. Input Frequency
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2007/04
[AKD4648-C]
AK4648 DAC => LINEOUT Linearity, fs=44.1kHz, fin=1kHz
+0 -5 -10 -15 -20 -25 -30 -35 -40 d B r A -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -100 -90 -80 -70 -60 -50 dBFS -40 -30 -20 -10 +0
Figure 32. Linearity
AK4648 DAC => LINEOUT Frequency Response, fs=44.1kHz, 0dB Input
+1 +0.8 +0.6 +0.4 +0.2 +0 -0.2 d B r A -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 20 -0.4 -0.6
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 33. Frequency Response
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2007/04
[AKD4648-C]
AK4648 DAC => LINEOUT FFT, fs=44.1kHz, 0dB Input
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 34. FFT Plot (Input level= 0dBFS)
AK4648 DAC => LINEOUT FFT, fs=44.1kHz, -60dB Input
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 35. FFT Plot (Input level = -60dBFS)
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2007/04
[AKD4648-C]
AK4648 DAC => LINEOUT FFT, fs=44.1kHz, No Signal
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 36. FFT Plot (No signal)
AK4648 DAC => LINEOUT Crosstalk, fs=44.1kHz, 0dB Input, red R=>L, blue L=>R
-80 -82 -84 -86 -88 -90 -92 -94 -96 -98 d B -100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 37. Crosstalk Plot
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2007/04
[AKD4648-C]
2-4 DAC (DAC HP(Single-ended Mode))(HPG=0dB)
AK4648 DAC =>HP (Single-end) THD + N vs Input Level , fs=44.1kHz, fin=1kHz
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -120
d B r A
-110
-100
-90
-80
-70
-60 dBFS
-50
-40
-30
-20
-10
+0
Figure 38. THD+N vs. Input Level
AK4648 DAC =>HP (Single-end) THD + N vs Input Frequency, fs=44.1kHz, 0dB Input
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 20
d B r A
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 39. THD+N vs. Input Frequency
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2007/04
[AKD4648-C]
AK4648 DAC => HP (Single-end) Linearity, fs=44.1kHz, fin=1kHz
+0 -5 -10 -15 -20 -25 -30 -35 -40 d B r A -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -100 -90 -80 -70 -60 -50 dBFS -40 -30 -20 -10 +0
Figure 40. Linearity
AK4648 DAC => HP (Single-end) Frequency Response, fs=44.1kHz, 0dB Input
+1 +0.8 +0.6 +0.4 +0.2 +0 -0.2 d B r A -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 2k 4k 6k 8k 10k Hz 12k 14k 16k 18k 20k -0.4 -0.6
Figure 41. Frequency Response
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2007/04
[AKD4648-C]
AK4648 DAC =>HP (Single-end) FFT, fs=44.1kHz, 0dB Input
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 42. FFT Plot (Input level= 0dBFS)
AK4648 DAC => HP (Single-end) FFT, fs=44.1kHz, -60dB Input
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 43. FFT Plot (Input level = -60dBFS)
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2007/04
[AKD4648-C]
AK4648 DAC => HP (Single-end) FFT, fs=44.1kHz, No Signal
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 44. FFT Plot (No signal)
AK4648 DAC =>HP (Single-end) Crosstalk, fs=44.1kHz, 0dB Input
-40 -45 -50 -55 -60 -65 -70 -75 d B -80 -85 -90 -95 -100 -105 -110 -115 -120 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 45. Crosstalk Plot
- 45 -
2007/04
[AKD4648-C]
2-5 DAC (DAC HP(Pseudo Cap-less Mode))(HPG=0dB)
AK4648 DAC =>HP (Pseudo Cap-less) THD + N vs Input Level, fs=44.1kHz, fin=1kHz
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -120
d B r A
-110
-100
-90
-80
-70
-60 dBFS
-50
-40
-30
-20
-10
+0
Figure 46. THD+N vs. Input Level
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2007/04
[AKD4648-C]
AK4648 DAC =>HP (Pseudo Cap-less) THD + N vs Input Frequencyl, fs=44.1kHz, 0dB Input
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 20
d B r A
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 47. THD+N vs. Input Frequency (Non invert signal input)
AK4648 DAC => HP (Pseudo Cap-less) THD + N vs Input Frequency, fs=44.1kHz, 0dB Input
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 20
d B r A
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 48. THD+N vs. Input Frequency (Invert signal input)
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2007/04
[AKD4648-C]
AK4648 DAC => HP (Pseudo Cap-less) Linearity, fs=44.1kHz, fin=1kHz
+0 -5 -10 -15 -20 -25 -30 -35 -40 d B r A -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -100 -90 -80 -70 -60 -50 dBFS -40 -30 -20 -10 +0
Figure 49. Linearity
AK4648 DAC => HP (Pseudo Cap-less) Frequency Response, fs=44.1kHz, 0dB Input
+1 +0.8 +0.6 +0.4 +0.2 +0 -0.2 d B r A -0.8 -1 -1.2 -1.4 -1.6 -1.8 20 50 100 200 500 Hz 1k 2k 5k 10k 20k -0.4 -0.6
Figure 50. Frequency Response
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2007/04
[AKD4648-C]
AK4648 DAC =>HP (Pseudo Cap-less) FFT, fs=44.1kHz, 0dB Input
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 51. FFT Plot (Input level= 0dBFS)
AK4648 DAC => HP (Pseudo Cap-less) FFT, fs=44.1kHz, -60dB Input
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 52. FFT Plot (Input level = -60dBFS)
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2007/04
[AKD4648-C]
AK4648 DAC => HP (Pseudo Cap-less) FFT, fs=44.1kHz, No Signal
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 53. FFT Plot (No signal)
AK4648 DAC=>HP (Pseudo Cap-less) Crosstalk, fs=44.1kHz, 0dB Input, red R=>L, blue L=>R
+0 -10 -20 -30 -40 -50 d B -60 -70 -80 -90 -100 -110 -120 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 54. Crosstalk Plot
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2007/04
[AKD4648-C]
2-6 DAC (DAC-->SP(Stereo))(SPKG2-0:+4.43dB)
AK4648 DAC =>SPK (stereo) THD + N vs Input Level, fs=44.1kHz, fin=1kHz
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -120
d B r A
-110
-100
-90
-80
-70
-60 dBFS
-50
-40
-30
-20
-10
+0
Figure 55. THD+N vs. Input Level
AK4648 DAC =>SPK (stereo) THD + N vs Input Frequency, fs=44.1kHz, 0dB Input
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 20
d B r A
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 56. THD+N vs. Input Frequency
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2007/04
[AKD4648-C]
AK4648 DAC =>SPK (stereo) Linearity, fs=44.1kHz,fin=1kHz
+0 -5 -10 -15 -20 -25 -30 -35 -40 d B r A -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -100 -90 -80 -70 -60 -50 dBFS -40 -30 -20 -10 +0
Figure 57. Linearity
AK4648 DAC =>SPK (stereo) Frequency Response, fs=44.1kHz, 0dB Input
+1 +0.8 +0.6 +0.4 +0.2 +0 -0.2 d B r A -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 20 -0.4 -0.6
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 58. Frequency Response
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2007/04
[AKD4648-C]
AK4648 DAC =>SPK (stereo) FFT, fs=44.1kHz, 0dB Input
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 59. FFT Plot (Input level= 0dBFS)
AK4648 DAC =>SPK (stereo) FFT, fs=44.1kHz, -60dB Input
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 60. FFT Plot (Input level = -60dBFS)
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2007/04
[AKD4648-C]
AK4648 DAC =>SPK (stereo) FFT, fs=44.1kHz, No Signal
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 61. FFT Plot (No signal)
AK4648 DAC =>SPK (stereo) Crosstalk, fs=44.1kHz, 0dB Input, red R=>L, blue L=>R
-70 -72.5 -75 -77.5 -80 -82.5 -85 -87.5 -90 -92.5 d B -95 -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 62. Crosstalk Plot
- 54 -
2007/04
[AKD4648-C]
AK4648 DAC =>SPK (stereo) Level (W) vs Amplitude Lch Green, Rch Yellow, THD + N vs Amplitude Lch Red, Rch Blue
+0 -10 -20 -30 -40 -50 d B -60 -70 -80 -90 -100 -110 -120 -60 1.2 1.1 1 .9 800m 700m 600m W 500m 400m 300m 200m 100m 0 -55 -50 -45 -40 -35 -30 dBFS -25 -20 -15 -10 -5 +0
Figure 63. THD+N & Output Power vs. Input Level (SPKG=+12.65dB)
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2007/04
[AKD4648-C]
2-7 DAC (DAC-->SP(High Power Mode))(SPKG2-0:+4.43dB)
AK4648 DAC =>SPK (High power) THD + N vs Input Level, fs=44.1kHz, fin=1kHz
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -120
d B r A
-110
-100
-90
-80
-70
-60 dBFS
-50
-40
-30
-20
-10
+0
Figure 66. THD+N vs. Input Level
AK4648 DAC =>SPK (High power) THD + N vs Input Frequency, fs=44.1kHz, 0dB Input
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 20
d B r A
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 67. THD+N vs. Input Frequency
- 56 -
2007/04
[AKD4648-C]
AK4648 DAC =>SPK (High power) Linearity, fs=44.1kHz, fin=1kHz
+0 -5 -10 -15 -20 -25 -30 -35 -40 d B r A -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -100 -90 -80 -70 -60 -50 dBFS -40 -30 -20 -10 +0
Figure 68. Linearity
AK4648 DAC =>SPK (High power) Frequency Response, fs=44.1kHz, 0dB Input
+1 +0.8 +0.6 +0.4 +0.2 +0 -0.2 d B r A -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 20 -0.4 -0.6
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 69. Frequency Response
- 57 -
2007/04
[AKD4648-C]
AK4648 DAC =>SPK (High power) FFT, fs=44.1kHz, 0dB Input
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 70. FFT Plot (Input level= 0dBFS)
AK4648 DAC =>SPK (High power) FFT, fs=44.1kHz, -60dB Input
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 71. FFT Plot (Input level = -60dBFS)
- 58 -
2007/04
[AKD4648-C]
AK4648 DAC =>SPK (High power) FFT, fs=44.1kHz, No Signal
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 72. FFT Plot (No signal)
AK4648 DAC =>SPK (High power) Level (W) vs Amplitude Green THD + N vs Amplitude Red
+0 -10 -20 -30 -40 -50 d B -60 -70 -80 -90 -100 -110 -120 -60 1.2 1.1 1 .9 800m 700m 600m W 500m 400m 300m 200m 100m 0 -55 -50 -45 -40 -35 -30 dBFS -25 -20 -15 -10 -5 +0
Figure 73. THD+N & Output Power vs. Input Level (SPKG=+12.65dB)
- 59 -
2007/04
[AKD4648-C]
Revision History
Date (YY/MM/DD) 07/03/19 07/04/13 Manual Revision KM088700 KM088701 Board Revision 0 1 Reason First Edition Parts Change Contents
AK4648 Rev.A Rev.B
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei EMD Corporation (EMD) sales office or authorized distributor concerning their current status. * EMD assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * EMD products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and EMD assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of EMD. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an EMD product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold EMD harmless from any and all claims arising from the use of said product in the absence of such notification.
- 60 -
2007/04
5
4
3
2
1
MPWR
LIN1
PDN
HPL
D
RIN3
SDTO
JP1 GND
MCKI
DGND
AGND
D
TVDD +
C1 10u
C2 0.1u
DVDD + C4 10u C5 0.1u
RIN3
R2 51
VCOC
JP2 51 R3 51 R4
R1 10k
C3 4.7n
AGND
D6
D3
D7
E1
E2
E3
E6
E7
F1
F2
U1
R5 51 SDTI
C
LIN1/IN1-
RIN3/VCOC
MPWR
DVDD
G7
R6 51
SDTO
PDN
TVDD
VSS1
VSS3
MCKI
HPL
F3
NC SDTI LRCK BICK MCKO TVDD NC CAD0 SCL RIN1/IN1+ ROUT/LON SDA HVDD SPRP
HPR MUTET AVDD LIN3/MIN LIN2/IN2+
D2 D1
AGND
G6 G5
C6 1u + C7 0.1u C8 10u
HPR
C
LRCK
C7 C6 C5 C4 C2
R7 51 BICK
G4 G3
R8 MCKO 51
G2 G1
AK4648
RIN4/IN4HVCM VSS2 VCOM RIN2/IN2NC NC
AGND
CAD0
F7 F6 F5 F4
C1 B7 B6 E5 E4
+ C9 0.1u C10 2.2u
B
B
R9 51 SCL
SPRN
SPLN
SPLP
TEST
VSS2
RIN1
LOUT/LOP
LIN4/IN4+
NC
NC
A1
A2
A4
A5
A6
A7
B1
B2
B3
B4
B5
D4
SDA
AGND
HVDD + C11 10u C12 0.1u
D5
NC
AGND
A
SPLP
SPRP
ROUT
SPRN
LOUT
SPLN
LIN4
AGND
5
4
3
+
AVDD MIN/LIN3 LIN2
RIN4
HVCM
RIN2
A
Title Size B Date:
2
AKD4648-C
Document Number
AK4648
Friday, March 30, 2007 Sheet
1
Rev 1 1 of 5
A
B
C
D
E
JP3 HPR Cap-less J1 LIN1/RIN1 6 + + 4 3 C13 1u RIN1 HPR C15 1u LIN1 + + HPL
C14 220u
+
R10
short
6 4 3 R11 J2 HP
E
E
+
JP4
R12 2.2k
C16 220u
C17 0.22u C18 0.22u JP5 HPL Cap-less
short
LIN1 JP7 R13 2.2k R14 10 R15 10
HVCM
JP6
GND
RIN1 JP8 LIN2
D
R16 2.2k
MPWR
HVCM R17 2.2k
D
JP9 RIN2 J3 LIN2/RIN2 6
C19 1u RIN2 +
4 3
C20 1u LIN2 +
TP1 SPLP
J4
SPK/L SPLN SPLP
JP10 High SPN 1 6 4 3 1 TP2 SPLN JP11 High SPP J6
C
C
C21 1u J5 MIN/LIN3/RIN3 6 4 3 RIN3 C22 1u + MIN/LIN3 R18 20k + LIN3 JP12
TP3 SPRP
SPK/R SPRN SPRP
1 6 4 3 1 TP4 SPRN
B
J8 LIN4/RIN4 6 4 3
+
C23 1u RIN4 C25 1u LIN4 + LOUT + R19 ROUT
C24 1u 6 4 3 JP13 LINEOUT
J7 LOUT/ROUT
B
A
+ 1u C26
open
A
Title Size A3 Date:
A B C D
AKD4648-C
Document Number
Input/Output
Sheet
E
Rev
1 2
of
Friday, March 30, 2007
5
A
B
C
D
E
D3V
1
L1
47u
PORT1
VCC
E
3 2 1
C27 + C28 R20 D3V
GND OUT
TORX141
2
0.1u
10u
E
470
C29 10u + C30 0.1u C31 10u + C32 4.7u R21 10k
TVDD
4 3 2 1
64
61
57
54
63
59
52
62
60
58
53
H L DIF1 5 DIF0 6 OCKS1 7 CAD0 8
SW DIP-4 S1
U2
AVSS
AVSS
56
55
51
50
ACKS
AVDD
AVDD
IPS0/RX4
AVDD
RXN0
D
1
VCOM
AVSS
P/SN
RX3
RX2
RX1
RXP0
R
49
DIF0/RX5
2
TEST
CAD0
3
DIF1/RX6
4 3 2 1
4115_PDN
4
PDN
5
RP1 47k
XSEL/RX7
6
C35 0.1u
DVDD
7
VIN
SDTO
8
DAUX
DVDD
41
9
C
DVSS
AK4115
OCKS0/CSN/CAD0
40
C
DIR_MCLK
10
MCKO1
OCKS1/CCLK/SCL
39
11
MCKO2
CM1/CDTI/SDA
38
12
OVDD
CM0/CDTO/CAD1
37
13
OVSS
INT1
36
DIR_BICK
14
BICK
INT0
35
DIR_SDTO
15
SDTO
ELRCK
34
DIR_LRCK C38 0.1u
16
LRCK EBICK
EMCK
33
OVDD
VOUT
B
OVSS
TVDD
XTO1
XTO2
TVSS
TXN1
TXP1
XTI1
XTI2
TX0
C
U
B
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
C39 0.1u
11.2896MHz 1 2 X1 5p C40 5p C42 + C41 0.1u
D3V 4115_MCKI JP14
PORT2
C43 10u
IN VCC GND
TOTX141
3 2 1
MCKO C44
0.1u
A
32
A
B
C
+
+
C33 0.1u
C34 0.1u
FILT
48
D
XTL1
47
XTL0
46
PSEL
45
IPS1/IIC
44
BVSS
43
DVSS
42
C36 0.1u C37 10u R22 5.1 D3V
INT0
B
A
Title Size A2 Date:
D
AKD4648-C
Document Number Friday, March 30, 2007
E
DIR/DIT
Sheet
Rev
1 3
of
5
A
B
C
D
E
JP15 MCLK
DIR_MCLK
JP16 BICK
DIR_BICK
U3
E
U4
E
MCKI SDTI SCL PDN
3 4 5 6 7 8 9 10 R100
A1 A2 A3 A4 A5 A6 A7 A8
B1 B2 B3 B4 B5 B6 B7 B8
21 20 19 18 17 16 15 14 47k
BICK LRCK RP2 6 5 4 3 2 1
3 4 5 6 7 8 9 10
A1 A2 A3 A4 A5 A6 A7 A8
B1 B2 B3 B4 B5 B6 B7 B8
21 20 19 18 17 16 15 14 6 5 4 3 2 1 47k RP3
JP17 LRCK
DIR_LRCK
1k
TVDD
SDA TVDD
D
AVC
C45 0.1u
D3V
1 2 11 12 VCCA DIR GND GND VCCB VCCB OE GND 24 23 22 13 C48 0.1u
D3V TVDD
D
C46 0.1u
1 2 11 12
VCCA DIR GND GND
VCCB VCCB OE GND
24 23 22 13 C47 0.1u
AVC
JP18 Signal V select
TVDD
Master
74AVC8T245
R24 AVC R23 R25 PORT3 10 9 8 7 6
JP19 DIR-SEL
74AVC8T245
Slave
10k 10k 470
C
1 2 3 4 5
SCL SDA
R30 1k R26 1k K
C
CTRL
D3V LED1 A ERF
MCLK BICK LRCK SDTI VCC 4115_PDN
1 2 3 4 5
PORT4 10 9 8 7 6
GND GND NC NC SDTO
DSP
R27
D3V
INT0
K R28 D1 A HSU119
D3V 10k
JP20 SDTO-IN
10k
1 2 3 4 5 6 C49
U5 1A 1Y 2A 2Y 3A 3Y 4Y 4A 5Y 5A 6Y 6A 8 9 10 11 12 13
L
3 1
B
H
SW1
ADC
JP21 SDTI
SDTO
B
PDN
2
0.1u
D3V
C50
14 7
Vcc GND 74HC14
DIR
DIR_SDTO
0.1u
A
A
Title Size A3 Date:
A B C D
AKD4648-C
Document Number Friday, March 30, 2007
LOGIC
Sheet
E
Rev
1 4
of
5
5
4
3
2
1
L4
(short)
2
VCC1
D
1
HVDD
1 2
T1
L2
T45_RED
10u
1
D3V
D
TA48033F
GND IN OUT C53
VCC
JP22 REG-SEL AVDD
1
REG 0.1u
+
2
AGND1 T45_BK
C51 47u
C52
R29 10 DVDD
0.1u
+ AGND
JP23 TVDD-SEL L3
1
1
AGND
C
TVDD1 T45_OR
(short)
1 2 1
TVDD
2
C54 47u
C
+
1 2
1
C55 47u
DGND1 T45_BK
B
B
A
A
Title Size B Date:
5 4 3 2
AKD4648-C
Document Number
POWER
Friday, March 30, 2007 Sheet
1
Rev 1 5 of 5

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